The present invention generally relates to an ATE (Automated Test Equipment). More particularly, the present invention relates to optimizing a test flow within an ATE.
An ATE station refers to any automated device that is used to test printed circuit boards, integrated circuits or any other electronic components. Agilent® Medalist i1000D, Agilent® Medalist i3070, Teradyne® Catalyst, Teradyne® Tiger, Teradyne® FLEX and Teradyne® UltraFLEX are examples of an ATE station.
A semiconductor manufacturing process requires a sequence of complex operations on each wafer to create multi-layered physical and electrical structures that form a desired very large scale integrated circuitry (VLSI). Defects in the process may occur due to several operational, mechanical or chemical control errors, or due to environmental uncertainty, e.g., contamination during the process. After manufacturing of semiconductor chips on each wafer is complete, a set of comprehensive electrical (e.g., a test for power consumption of each semiconductor chip on each wafer), functional (e.g., a behavioral test on each semiconductor chip on each wafer), and characterization tests (e.g., tests measuring area or clock frequency of semiconductor chip on each wafer) are performed to determine an actual wafer and semiconductor chip yield. These tests require several detailed measurements of various electrical parameters, using different test configurations. An automated test equipment (ATE) station operates a sequence of such tests on all pins on all semiconductor chips on each wafer. Additional stages of tests may then be performed by other ATE stations to simulate different environmental settings, or measure different parameters etc. An end-to-end test process (i.e., process running all tests on every semiconductor chip) consumes a significant amount of time, and it is critical that the process be optimized appropriately. Optimization of the test process involves an appropriate scheduling of wafers and lots onto multiple ATE stations and across stages of test settings in order to optimally utilize testers and maximize test throughput.
It would be desirable that the optimization of the test process includes an optimization of a test flow within each ATE station to minimize a time to detect any defects or failures on a semiconductor chip or a wafer.